Combination flash memory and dram memory board interleave-bypass memory access method, and memory access device incorporating both the same
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United States of America Patent
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Oct 12, 1999
Grant Date -
N/A
app pub date -
Jun 16, 1997
filing date -
Jul 12, 1996
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A memory board which functions as a main memory of a CPU, is accessible at high speed and is usable in a disk manner is proposed. A flash memory and a D-RAM are mounted on the memory board. The flash memory has a S-RAM interface which synthesizes a row address and a column address transmitted via an address bus, through a latch circuit or a signal processing circuit, to define an address. The CPU, when accessing an address in the flash memory, converts an address signal using an interleave rule in reverse, and transmits the converted address to a system logic. As a result, data can be written into contiguously allotted addresses in the flash memory. The flash memory can thus be used in a disk-like manner.
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