Flip-flop circuit, parallel-serial converting circuit, and latch circuit
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United States of America Patent
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Oct 19, 1999
Grant Date -
N/A
app pub date -
Jul 15, 1997
filing date -
Mar 5, 1997
priority date (Note) -
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status (Latency Note)
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Abstract
It is an object to enlarge the logical amplitude of an output signal of a flip-flop circuit with a suppressed, low power-supply voltage to reduce the possibility of occurrence of malfunction. A signal outputted from a differential amplification portion is converted in an internal level converting circuit and fed back to bases of transistors of a slave latch. With input signals having a high level at 0.5 V, the internal level converting circuit performs conversion to provide output signals having a high level at 0.25 V to prevent a current flowing between a collector and a base of the transistors.
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