Importance

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Abstract

A delay circuit having standby state and active state and designed to output at least one signal obtained by delaying an input signal. The delay circuit comprises a storage circuit and at least one amplifier circuit. In operation, the storage circuit receives an input signal, generates a first voltage when the input signal is inverted, and generates a second voltage from a difference between the first voltage and a first supply voltage. The amplifier circuit amplifies the difference between the first voltage and the second voltage. The storage circuit includes at lease one constant-voltage generating section for generating the first voltage when the input signal is inverted, at least one constant-current generating section for generating a current proportional to the difference between the first voltage and the first supply voltage, and at least one capacitor having a first terminal set at the first supply voltage or a second supply voltage, and a second terminal charged to the first supply voltage while the delay circuit remains in the standby state and charged or discharged to the second voltage with the current generated by the constant-current generating section while the delay circuit remains in the active state.

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First Claim