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Abstract

A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a low dielectric constant dielectric layer, where the low dielectric constant dielectric layer is formed from a silsesquioxane spin-on-glass (SOG) dielectric material. There is then formed over the low dielectric constant dielectric layer a patterned photoresist layer. There is then etched through use of a fluorine containing plasma etch method while employing the patterned photoresist layer as a photoresist etch mask layer the low dielectric constant dielectric layer to form a patterned low dielectric constant dielectric layer having a via formed therethrough. The fluorine containing plasma etch method employing a fluorine containing etchant gas composition which simultaneously forms a fluorocarbon polymer residue layer upon a sidewall of the via. There is then treated through use of a plasma treatment method the fluorocarbon polymer residue layer to form a plasma treated fluorocarbon polymer residue layer. The plasma treated fluorocarbon polymer residue layer is susceptible, in comparison with the fluorocarbon polymer residue layer, to being stripped from the sidewall of the via through an oxygen containing plasma stripping method employed in stripping from the microelectronics fabrication the patterned photoresist layer with attenuated lateral etching of the patterned low dielectric constant dielectric layer. Finally, there is then stripping through use of the oxygen containing plasma stripping method the patterned photoresist layer from over patterned low dielectric constant dielectric layer and the plasma treated fluorocarbon polymer residue layer from upon the sidewall of the via.

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