Reticle and method of design to correct pattern for depth of focus problems

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United States of America Patent

PATENT NO 5972541
SERIAL NO

09035110

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Abstract

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A method and apparatus for converting a layout design for the metallization layer integrated circuit pattern to a reticle design having corrections for depth of focus problems. The apparatus includes a design rule checker which is configured to identify locations of the layout design which are expected to produce narrowed regions of the image caused by depth of focus variations at intersections between defined line features of the layout design and the elevated portions of the topographical variations. A depth of focus correction unit is included which is adapted to modify the layout design for the metallization integrated circuit pattern at the locations by increasing the line width of the defined line features from the integrated circuit pattern to correct for these depth of focus problems.

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Patent Owner(s)

Patent OwnerAddress
BELL SEMICONDUCTOR LLC401 N MICHIGAN AVE SUITE 1600 CHICAGO IL 60611

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Garza, Mario Sunnyvale, CA 31 1774
Sugasawara, Emery O Pleasanton, CA 13 401

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