Test circuit and method of trimming a unary digital-to-analog converter (DAC) in a subranging analog-to-digital converter (ADC)
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United States of America Patent
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Oct 26, 1999
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N/A
app pub date -
Jan 20, 1998
filing date -
Jan 20, 1998
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Abstract
In a subranging ADC, the unary DAC is trimmed by walking through its transfer function while toggling an offset cell at the input to the coarse quantizer and a reference cell in the DAC such that the reference cell is substituted for the cell under test on alternating cycles to provide the last lsb of the reconstructed signal. A test circuit measures the voltage at the output of the summing amplifier for both conditions and generates an error voltage in which the common mode terms have been rejected. The cell under test is then laser trimmed to reduce the error voltage until the cell's DNL error is within an error bound of a tolerance. In one embodiment, the tolerance is dithered to improve spur free dynamic range.
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