Reduced terminal testing system
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United States of America Patent
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Nov 2, 1999
Issued Date -
N/A
app pub date -
Oct 10, 1997
filing date -
Sep 13, 1996
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer. In a preferred embodiment, the conductive path simultaneously carries a VCC power signal and the alternating signal to the circuitry. However, the alternating signal may be carried on a conductive path different from the one carrying the VCC signal. A great deal of information may be conveyed through the alternating signal, making other signals unnecessary in controlling, testing, stressing, and repairing dice on the wafer. For example, clocking information may be conveyed through the alternating signal. The circuitry may be placed in different modes in response to different characteristics of the alternating signal. The alternating signal and a VCC power signal are received through a single contact on each die. A wafer mode controlling system includes a system controller to control application of the alternating signals and other signals to the dice on the wafer. The semiconductor wafer mode controlling system may also control a probe positioning controller including an array of probes that selectively brings the probes into contact with the probe pads, whereby the alternating signal having the certain characteristics is transmitted from the probe to the circuitry through the probe pad and conductive path and the circuitry of each of the dice is placed into the mode.
First Claim
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- 15 United States
- 10 France
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- 2 Other
Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| U S BANK NATIONAL ASSOCIATION AS COLLATERAL AGENT | 100 WALL STREET SUITE 1600 NEW YORK NY 10005 |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Beffa, Raymond J | Boise, ID | 63 | 1341 |
| Cloud, Eugene H | Boise, ID | 92 | 3562 |
| Farnworth, Warren M | Nampa, ID | 855 | 33798 |
| Nevill, Leland R | Boise, ID | 63 | 1548 |
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| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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