High density gate array cell architecture with sharing of well taps between cells
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United States of America Patent
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Nov 2, 1999
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N/A
app pub date -
Mar 28, 1997
filing date -
Mar 28, 1997
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Abstract
An arrangement and method for making a gate array architecture locates the well taps at the outer corners of each gate cell. The power buses are also located at the outside of the gate cell as well, enabling sharing of the well taps and the power buses. The location of the well taps at the outside corners of the standard cell reduces the number of transistors in a single repeatable cell from eight transistors to four transistors.
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