Circuit board testing method
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United States of America Patent
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Nov 2, 1999
Grant Date -
N/A
app pub date -
Jan 8, 1998
filing date -
Jan 9, 1997
priority date (Note) -
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status (Latency Note)
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Abstract
The invention relates to a circuit board testing method, wherein an array of several circuits of a circuit board are short-circuited and further circuits are short-circuit tested by applying a high test voltage relative to said array of circuits, as a result of which the number of tests, which are normally highly time-intensive due to the high voltages, is drastically reduced since the further circuits do not need to be tested discretely relative to each circuit of the circuit array.
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