Differential MOS current-mode logic circuit having high gain and fast speed
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United States of America Patent
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Nov 2, 1999
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N/A
app pub date -
Oct 20, 1997
filing date -
Oct 20, 1997
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Abstract
The differential MOS current-mode logic structure of the present invention is comprised of a differential MOS transistor pair and a complementary MOS (CMOS) transistor for each of the transistors comprising the differential MOS pair. The gates of the CMOS transistors are coupled to the gates of the differential MOS pair. Since the gates of the differential MOS pair receive a differential signal from the inputs, the voltage between the gate and the source, Vgs, for each of the transistors comprising the MOS differential pair is not fixed. As a result, the gain of the CMOS current-mode logic structure of the present invention is high. In addition, since the gates of the CMOS transistors are coupled to the gates of the differential MOS pair, the current for the CMOS transistors is increased when charging the node capacitance and is decreased when discharging the node capacitance. Hence, the present invention allows faster charging and discharging of transistors, which results in faster switching transistors and higher speed circuit.
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