STAR-I: scalable tester architecture with I-cached SIMD technology
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United States of America Patent
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Nov 2, 1999
Grant Date -
N/A
app pub date -
Mar 26, 1997
filing date -
Dec 19, 1996
priority date (Note) -
Expired
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Abstract
A semiconductor tester high-speed system with Single Instruction-stream Multiple Data-stream (SIMD) organization, incorporating an event generator array, a plurality of pin channels for connecting to a device under test (DUT), a reconfigurable allocation switch for assignment of event generators to individual DUT pin channel connections, multi-clocking, and SIMD instruction cache. The result is a tester digital system exhibiting a maximum ratio of performance to hardware cost.
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