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Abstract

An on-the-fly error detection and correction hardware core for a mass storage hard disk drive comprises a microcode machine optimized and limited to doing Galois Field arithmetic (GF[2.sub.8 ]) in support of Reed-Solomon error detection and correction (RS-EDC). The microcode machine is implemented as a hardware core in a system-on-a-chip design that includes a general purpose core RISC-processor. A dual-input arithmetic logic unit (ALU) includes a set of basic arithmetic blocks necessary to support the RS-EDC operations, i.e., a multiplier, a dedicated adder, a general purpose adder, a divider, a log unit, a quadratic solution lookup, a cubic solution lookup, and a move datapath. The operations and outputs of all the basic arithmetic blocks are presented in parallel to an op-code selector. The selected output is routed back for deposit to one of eight general purpose registers (R0-R7). A set of up to eight syndrome registers (S0-S7) can be selectively routed along with R0-R7 through a pair of ALU-input selectors. A microinstruction register allows a destination register decoder to be controlled, instruction-by-instruction, as well as the ALU input and output selectors. The microcode program is stored in a ROM-type structure that is indexed by a program counter. A flow control selector allows either the next microprogram address (+1) to be selected from an incrementer, or a branch address to be selected from a jump table.

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First Claim