Programmable logic device architectures
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United States of America Patent
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Nov 9, 1999
Grant Date -
N/A
app pub date -
Jun 11, 1997
filing date -
Feb 20, 1997
priority date (Note) -
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status (Latency Note)
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Abstract
A programmable logic device has regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Horizontal interconnection conductors are associated with each row, and vertical interconnection conductors are associated with each column. Local conductors are interspersed between adjacent pairs of regions in each row for supplying signals to the regions on both sides of the local conductors. Subregions of programmable logic in each region generally have a local output and a global output. The global output is only usable to output to the relatively long-distance horizontal and vertical conductors. The local output is additionally usable as a local feedback and as a local connection to an adjacent region.
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