Parallel-to-serial CMOS data converter with a selectable bit width mode D flip-flop M matrix
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United States of America Patent
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Nov 9, 1999
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app pub date -
Jan 9, 1998
filing date -
Jan 9, 1998
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Abstract
A high-speed parallel-to-serial CMOS data transmitter uses a D Flip-flop matrix architecture to combine a shift scheme with a selection scheme to serialize parallel bit data. Data is partially serialized through multi data paths at a much lower frequency and a time-division multiplex scheme selects one bit from each data path allowing for pipelined data processing. The CMOS architecture uses selective load clock mode switching allowing different word bit widths to be processed simply by adjusting the frequency of a loading clock.
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