Circuit and method for biasing the charging capacitor of a semiconductor memory array
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United States of America Patent
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Nov 9, 1999
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N/A
app pub date -
Dec 18, 1997
filing date -
Dec 18, 1997
priority date (Note) -
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Abstract
The cathode of the charging capacitor (31) of the present invention is coupled to a switch (36) that is able to apply one of several voltage levels to the cathode depending on the testing or use condition of the semiconductor memory array (10). The switch switches between the voltage levels at the cathode to avoid overstressing the charging capacitor (31) during testing of the semiconductor memory array (10).
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