Importance

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Abstract

A DMA controller has a first data buffer and a second data buffer. First data from a first bus can be loaded into the first data buffer at the same time that second data from a second bus is loaded into the second data buffer. Once the data is present in the first and second data buffers, the first data in the first data buffer can be supplied to the second bus at the same time that the second data in the second data buffer is supplied to the first bus (or alternatively to a third bus). In some embodiments, the second bus is a high speed parallel bus and the first and third data buses are I/O data buses for coupling the DMA controller to codecs. In some embodiments, data from the first data bus can be loaded into the first data buffer at the same time that data in the second data buffer is supplied to the third data bus. An address generator generates addresses onto the second data bus for the transfer of data between the DMA controller and the second data bus.

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First Claim