Circuit and method for controlling bit line for a semiconductor memory device
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United States of America Patent
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Nov 9, 1999
Grant Date -
N/A
app pub date -
Dec 23, 1997
filing date -
Jan 30, 1997
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A first precharge circuit precharges a bit line to an equalization voltage during precharging operations and is disabled during charge sharing operations floating the bit line. A second precharge circuit precharges a bit line bar to an equalization voltage during precharging and charge sharing operations. Since the bit line is floated during charge sharing operations, and the bit line bar is continually precharged to an equalization voltage level, variation of the bit line bar voltage level due to a charge coupling between the bit line and the bit line bar during charge sharing is prevented. The difference in a level between the bit line and the bit line bar after the charge sharing can be detected by a sense and amplification circuit.
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