Importance

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Abstract

First and second slotlines are mounted on an electrically insulating substrate having a planar face with a connection region. Each slotline has first and second, spaced-apart coplanar conductors that extend into the connection region. A fifth, ground conductor, also mounted on the substrate face, is spaced from and coplanar with the first and second slotlines and has a proximal portion in the connection region. A chip circuit includes first and second field-effect transistors (FETs) flip mounted in the connection region to all five conductors. The gates of the FETs are connected to the first slotline for receiving an input signal. The drains are connected to the second slotline for outputting the signal amplified by the transistors. The sources of the FETs are connected to the fifth conductor. This general configuration can be modified for use as an amplifier, oscillator, frequency multiplier or mixer. The slotline may divide into parallel slotline portions for providing plural circuits in parallel with distributed impedance matching. A slotline may loop back from the connection region to provide a choice for impedance matching, and a portion of the fifth conductor may extend between slotline conductors to provide capacitive coupling.

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First Claim