Power down system and method for pipelined logic functions
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United States of America Patent
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Nov 9, 1999
Grant Date -
N/A
app pub date -
Aug 21, 1995
filing date -
Aug 21, 1995
priority date (Note) -
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Abstract
Logic circuitry added to each stage of a pipeline of staged logic circuitry sequentially removes a clock signal from each stage when data incoming to the pipeline is invalid, or not to be processed for any practical use. The same logic circuitry is also useful for reapplying the clock signal to the successive stages of the pipeline when valid data is to be processed by the pipeline.
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