Importance

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Abstract

A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ('AGP') bus device such as an AGP graphics controller, and a host processor and computer system memory wherein AGP transaction read requests are merged from the AGP graphics controller and retired when these requests are within a cacheline of the memory being accessed. The core logic chipset will request a memory cacheline read as it begins processing a current AGP transaction read request. Once the memory read access is initiated, the transaction read request will be popped off an AGP request queue in order to evaluate the next in order transaction request. If the next request can be partially or completely retired by the memory read access previously started, then the memory access that would have been normally required may be skipped and the data from the previous memory read access is used instead. This AGP read transaction merging may continue until the next in order transaction read request is located in a different cacheline of memory or the original memory request is ready to return data. A memory data buffer may also be utilized to store unused quadwords of the cacheline read from a memory access so that some subsequent AGP transaction requests may be retired without having to access a previously read cacheline of memory.

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First Claim