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Abstract

The threshold voltage distribution for write operation into memory cells of a multi-level nonvolatile semiconductor memory device is precisely controlled and the verify result of written data is simultaneously detected for each page. For example, at the '10' data write time, excess write of '00' data which is a conventional problem is inhibited by controlling a path for transferring a lower bit to a bit line according to an upper bit. Further, at the write-verify time, the verify result can be simultaneously detected for each page by controlling the verify operation according to the upper bit. At the write time of '01' data, the bit line path is controlled by use of the lower bit and the write operation of '00' data is inhibited. Also, at the write-verify time, the verify result can be simultaneously detected for each page by controlling the verify operation according to the lower bit. The write and verify operations of '00' data can be effected in the same manner as in the case of '01' data by first inverting the lower bit of '00' data. Since the write operation can be effected while all of the write states of a plurality of bits are verified, each level of written data can be precisely controlled without causing excess or insufficiency in the threshold voltage after the write operation into the memory cell. Further, since the verify result can be simultaneously detected for each page, time can be significantly reduced.

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