Apparatus and method for operably connecting a processor cache and a cache controller to a digital signal processor
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United States of America Patent
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Nov 16, 1999
Grant Date -
N/A
app pub date -
May 8, 1997
filing date -
Jan 10, 1997
priority date (Note) -
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Abstract
A peripheral module capable of interaction with a host system comprises a digital signal processor (DSP), a cache controller, and minimal or no resident memory for initial storage of instructions and data. The peripheral module utilizes the memory resources (e.g., ROM and RAM) of a host system. The cache controller interfaces to the DSP and provides an instruction and data stream, upon request, from a resident cache. A bus interface unit arbitrates access to the host system via a host bus for access to host system resources by the cache controller for extracting DSP information (e.g., instructions and data) from the host system for utilization by the DSP within the peripheral module. The cache controller and cache thereby provide the instruction and data stream as required by the DSP for digital signal processing applications and relieve the need for resident storage within the peripheral module.
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