Importance

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Abstract

An apparatus called a DataPort is disclosed for use in conjunction with a computer. The DataPort includes a private memory comprised of a high-speed, solid-state random access memory array. A public memory comprising a series of registers serves as an intermediary between the private memory array and a computer CPU local bus for memory access operations. The public memory includes staging registers which are used for conversion between the CPU local bus word size and the internal private memory word size as may be necessary, including pipelining as required. The DataPort also generates error correction codes (ECC) and stores the correction codes in the private memory, interleaved with data received from the CPU local bus, and checks the ECC codes to detect errors when data is read back out to the bus. The DataPort has the advantages of providing a high-speed, variable packet length, error-corrected access to a memory array at the CPU local bus operating speed, so that the device can be used with no wait states for improved throughput in a computer system.

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First Claim