Captured-cell solder printing and reflow methods
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United States of America Patent
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Nov 23, 1999
Grant Date -
N/A
app pub date -
May 27, 1997
filing date -
May 27, 1997
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Abstract
Methods for forming solder bumps on integrated circuit chips (and other similar circuitized units). A screening stencil is laid over the surface of the substrate and solder paste material is deposited into the stencil's apertures with a screening blade. The stencil is placed in such a manner that each of its apertures is positioned over a substrate pad, upon which a solder bump is to be formed. Next, a flat pressure plate is laid over the exposed top surface of the stencil, which creates a fully enclosed or 'captured', cell of solder paste within each stencil aperture. Then, with the stencil and plate remaining in place on top of the substrate, the substrate is heated to a temperature sufficient to reflow the solder paste material. After reflow, the substrate is cooled, and the pressure plate and stencil are thereafter removed, leaving solder bumps on the substrate. The use of the pressure plate ensures the proper formation of the solder bumps at high densities of solder bumps (i.e., high densities corresponding to small solder bump sizes and small pitch distances between solder bumps).
First Claim
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
- FUJITSU LIMITED;SEMIPAC, INC.;SEMI-PAC
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- [Patents Count]
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Boucher, Patricia R | Fremont, CA | 4 | 142 |
Love, David G | Pleasanton, CA | 17 | 825 |
MacKay, John T | San Jose, CA | 3 | 46 |
Molinaro, Thomas E | Newark, CA | 2 | 41 |
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Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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