Method of customizing integrated circuits by depositing two resist layers to selectively pattern layer interconnect material
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 23, 1999
Issued Date -
N/A
app pub date -
Mar 12, 1998
filing date -
Mar 24, 1997
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method for fabricating custom integrated circuits includes the steps of 1) patterning a photoresist layer on an insulative layer with a standard via precision mask to define all possible vias, and 2) using a targeting energy beam to select the desired via locations on a second photoresist layer, which are then etched and interconnections made, for customization or repair of the integrated circuit. Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully