Process of manufacturing compliant wirebond packages
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United States of America Patent
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-
Nov 23, 1999
Grant Date -
N/A
app pub date -
Dec 12, 1997
filing date -
Dec 13, 1996
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method of making a assembly including the steps of fitting a chip within an aperture in a frame, connecting the bond pads on the frame to the contacts on the chip by forming wire loops therebetween, dispensing a compliant material over the frame, chip and wire loops for form a compliant layer, and plasma etching the top surface of the compliant layer to expose the top portion of each wire loop. The semiconductor chip assembly can then be incorporated into a larger assembly by connecting the wire loops to connection pads on an external substrate.
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