Monolithic circuit and method for adding a randomized dither signal to the fine quantizer element of a subranging analog-to digital converter (ADC)
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United States of America Patent
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Nov 23, 1999
Grant Date -
N/A
app pub date -
Sep 30, 1997
filing date -
Sep 30, 1997
priority date (Note) -
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Abstract
A dither circuit is monolitically integrated with a subranging ADC to add a dither signal at the input of the ADC's fine quantizer element to randomize its nonlinear quantization level errors. Because the subranging ADC has at least one overlap bit, the amplitude of the dither signal can range up to at least 2.sup.M-1 LSBs of the fine quantizer without saturating it. The digital equivalent of the dither signal is subtracted at the output of the fine quantizer to maintain the ADC's overall SNR. The randomization of only the fine quantizer element avoids gaining up the nonlinear errors associated with the dither signal itself thereby improving the overall SNR. This approach optimizes performance for small input signals while sacrificing flexibility to correct other sources of error.
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