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Abstract

A video controller in a graphic accelerators suitable for use in three dimensional graphics and texture mapping is disclosed. The controller includes an address generator for generating addresses for reading out texture data stored in the video memory and a mode register for generating a directional signal for prefetching the texture data. A prefetch controller is provided to produce an address for another texture data predicted to be used at the next time, based on the directional signal supplied from the mode register and the address of the address generator. Also provided are a memory controller for accessing the texture data corresponding to the address generated in the prefetch controller via the memory interface, and a buffer memory for storing the prefetched texture data outputted from the memory controller and the address of the prefetched texture data. Further, the prefetching method comprises the steps of determining whether the address generated at the address generator is identical with the one stored in the buffer memory; outputting the texture data stored in the buffer memory if said two addresses are identical and determining whether prefetching of the texture data is possible; addressing the texture data corresponding to the address provided by the address generator, if two addresses are not identical; prefetching a texture data predicted to be used next time in the video memory based on the directional signal supplied from the mode register and the address supplied from the address generator, if the prefetching is possible; and storing the prefetched texture data and its corresponding address into the buffer memory. The video controller of this invention considerably reduces the time required for accessing the video memory since prefetched texture data is read out in the internal buffer register without accessing the same in the outer video memory.

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First Claim