Method for reducing program disturb during self-boosting in a NAND flash memory

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United States of America Patent

PATENT NO 5991202
SERIAL NO

09161423

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Abstract

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A NAND flash memory system is programmed with minimal program disturb and pass disturb during self-boosting without resorting to impurity implantation for bit line isolation, to p-well biasing or to bit line biasing techniques. A program voltage is applied to a selected word line in the form of a plurality of short pulses while synchronously applying a pulsed pass voltage to the unselected word lines until the selected cell is programmed. The duration of the pulses and the time between pulses are chosen to minimize the program disturb of unselected cells, especially unselected cells on the selected word line, without causing pass disturb of any cell in the array.

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Patent Owner(s)

Patent OwnerAddress
MONTEREY RESEARCH LLC3945 FREEDOM CIRCLE SUITE 900 SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Derhacobian, Narbeh Belmont, CA 65 1968
Fang, Hao Cupertino, CA 127 1556

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