Memory transactions on a low pin count bus
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United States of America Patent
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Nov 23, 1999
Grant Date -
N/A
app pub date -
Sep 24, 1997
filing date -
Sep 24, 1997
priority date (Note) -
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Abstract
A system having a bus coupled to a host and a memory device. The bus may include a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The memory device may store system start-up information and communicate this information with the host over the bus.
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