Cache ram using a secondary controller and switching circuit and improved chassis arrangement
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United States of America Patent
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Nov 23, 1999
Grant Date -
N/A
app pub date -
Oct 28, 1996
filing date -
Oct 28, 1996
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Abstract
A memory system including a main memory such as a cache memory and a shadow or back-up cache memory in conjunction with a write cache is disclosed. The shadow memory is coupled to the same data bus as the main memory and is written to simultaneously. Thus, there is no latency between writing to the main memory and writing to the shadow memory. Redundancy is provided for by having a switching circuit which allows control of the shadow memory to be transferred to a second controller upon failure of a first controller. A unique layout arrangement for a RAID (redundant array of independent disks) chassis is also described in which back-to-back circuit boards are mounted in the center of the chassis and a main bus on one board becomes the shadow bus on the other board, providing a mirror arrangement for the circuit boards.
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