Methods for accessing coincident cache with a bit-sliced architecture
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United States of America Patent
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Nov 23, 1999
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app pub date -
Nov 13, 1997
filing date -
Jul 15, 1993
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Abstract
A 'bit-sliced' construction of our cache module dictates dual TAG RAM structures and dual invalidation queues, yielding enhanced performance. By putting half the TAG array in each of two cache arrays, and allowing each to handle only one-half of the possible address values, processor operations and invalidation operations can be 'overlapped', and even operate simultaneously.
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