MPEG motion compensation using operand routing and performing add and divide in a single instruction
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United States of America Patent
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Nov 23, 1999
Grant Date -
N/A
app pub date -
Dec 31, 1996
filing date -
Dec 31, 1996
priority date (Note) -
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Abstract
A routable operand and selectable operation processor multimedia extension unit is employed to motion compensate MPEG video using improved vector processing. A vector processing unit executes an add and divide instruction that adds two vector registers and divides the result in a single instruction. This is implemented through loading a first vector register with a first plurality of elements from a source block. A second vector register is then loaded with a second plurality of elements that are adjacent to the first plurality of elements. The add and divide instruction is then executed on the first and second vector registers, yielding an interpolated source element that is stored in a resultant vector register.
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