Flip chip circuit arrangement with redistribution layer that minimizes crosstalk
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United States of America Patent
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Nov 30, 1999
Grant Date -
N/A
app pub date -
Sep 21, 1998
filing date -
Sep 21, 1998
priority date (Note) -
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Abstract
A circuit arrangement for a flip chip utilizes fixed potential shield traces between various signal traces in a redistribution layer to decrease coupling impedances and crosstalk within the layer. In particular, by orienting a fixed potential shield trace between a pair of signal traces and/or between a pair of differential trace pairs, capacitive coupling between the traces is greatly reduced, thereby permitting the signal traces to be routed closer to one another than would be possible if the shield trace was omitted. Often, minimum line width and spacing design rules may be met to ensure maximum circuit density for the redistribution layer and the associated device interconnections, and without concern for excessive adverse effects due to capacitive coupling between traces in the redistribution layer.
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