Semiconductor chip package with dual layer terminal and lead structure
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United States of America Patent
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Nov 30, 1999
Grant Date -
N/A
app pub date -
May 29, 1998
filing date -
May 30, 1997
priority date (Note) -
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Abstract
An assembly for packaging a microchip has a dielectric element including a top dielectric layer having a bottom surface. Traces extend at the bottom surface to connect terminals of the dielectric layer to conductive elements, the conductive elements being connected to contacts on a chip. Each trace has a terminal to which it is electrically connected. Traces extend beneath terminals to which they are not electrically connected.
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