Synchronous memory test system
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United States of America Patent
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Nov 30, 1999
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N/A
app pub date -
Jul 16, 1997
filing date -
Jul 16, 1997
priority date (Note) -
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Abstract
An automated, portable, and time conservative memory test system for identifying test parameters including type, control line configuration, depth, width, access time, and burst features of any one of a wide variety of synchronous memories including SDRAMs and SGRAMs, and whether an IC chip, bank, board or module, without requiring hardware modifications or additions to the memory device being identified, and without requiring storage of test patterns or characterizing, data in the memory device.
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