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Abstract

A high speed memory interface for a processor-based computing system provides a bridge component (made up of a controller and a data path), one or more data multiplexer/buffers, and a plurality of RAS/CAS generators. The high speed memory interface allows for the expansion of the memory subsystem without additional loading on the processor/system bus and without a reduction in memory transaction performance. The interface includes a single controller for receiving memory transaction commands from the processor/system bus, and a plurality of RAS/CAS generators, for generating RAS/CAS signals in response to memory transaction commands forwarded by the controller. Each RAS/CAS generator is coupled to one or more memory banks. A data multiplexer/buffer is coupled to one or more of the memory banks, and provides an interface between the memory bank(s) and the data path.

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First Claim