Inclusion vector architecture for a level two cache
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United States of America Patent
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Nov 30, 1999
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N/A
app pub date -
Jun 20, 1997
filing date -
Jun 20, 1997
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Abstract
A cache architecture with a first level cache and a second level cache, with the second level cache lines including an inclusion vector which indicates which portion of that line are stored in the first level cache. In addition, an instruction/data bit in the inclusion vector indicates whether a portion of that line is in the instruction cache at all. Thus, when a snoop is done to the level two cache, additional snoops to the level one cache only need to be done for those lines which are indicated as present by the inclusion vector.
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