Integrated CMOS circuit arrangement and method for the manufacture thereof
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United States of America Patent
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Dec 7, 1999
Grant Date -
N/A
app pub date -
Sep 9, 1997
filing date -
Sep 27, 1996
priority date (Note) -
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Abstract
Semiconductor islands respectively comprise at least a Si.sub.1-x Ge.sub.x layer and a distorted silicon layer that exhibits essentially the same lattice constant as the Si.sub.1-x Ge.sub.x layer are formed on an insulating layer that is located on a carrier plate. The semiconductor islands are preferably formed by selective epitaxy and comprise p-channel MOS transistors and/or n-channel MOS transistors.
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