Architectures for programmable logic devices
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United States of America Patent
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Dec 7, 1999
Grant Date -
N/A
app pub date -
Aug 28, 1997
filing date -
Oct 10, 1996
priority date (Note) -
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Abstract
A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Each super-region may be like a small or moderately sized programmable logic device and may include a two-dimensional array of intersecting rows and columns of regions of programmable logic. Each region may in turn include a plurality of subregions of programmable logic. Horizontal and vertical inter-super-region interconnection conductors are associated with the rows and columns of super-regions. These conductors are selectively connectable to horizontal and vertical inter-region interconnection conductors in the super-regions.
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