Circuit arrangement with combinatorial blocks arranged between registers
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United States of America Patent
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Dec 7, 1999
Grant Date -
N/A
app pub date -
Sep 26, 1997
filing date -
Sep 27, 1996
priority date (Note) -
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status (Latency Note)
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Abstract
Combinatorial blocks (KBL) are arranged between an input register (RG1) and output register (RG2) in the circuit arrangement. The input (E.sub.-- RG1) and the output (A.sub.-- RG1) of the input register (RG1) connected preceding the combinatorial blocks (KBL) is connected to a comparison unit (COM) that compares the value at the input and at the output of the input register (RG1) and, given occurrence of a signal value change at the input, outputs a control signal for loading the output value of the combinatorial blocks (KBL) into the output register (RG2) connected following the combinatorial blocks. In this way, the running time required for an operation in the circuit arrangement can be shortened given specific value combinations.
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