Importance

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Abstract

A system, apparatus and method which functions to restrain over-eager load boosting in an out-of-order processor through the implementation of a special 'coloring' mechanism that colors dependent load and store instructions to ensure recognition of a dependency based on the assignment of a common multi-bit 'color' scheme. In an exemplary embodiment, two bits of color are assigned to load and store instructions. These color bits are stored in a special array and are read when the load or store is read from the instruction cache ('I$'). The encoding of '00' for a load, for example, may indicate no coloring dependency for the load. Any encoding other than a '00' is utilized to indicate a store-load dependence for a store and load of the same color. The color bits for the load and store instructions are updated when a read-after-write ('RAW') hazard is detected by the memory disambiguation buffer ('MDB') for a store-load pair. The processor dependency tracking logic will enforce a dependency between a store and load of the same color (other than '00') and the instruction scheduling window ('ISW') will not boost the load past the store. Moreover, the instruction scheduling window will schedule the load for fetching data from the memory disambiguation buffer rather than the data cache ('D$').

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First Claim