Parallel prefix operations in asynchronous processors
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United States of America Patent
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Dec 7, 1999
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N/A
app pub date -
Sep 15, 1997
filing date -
Sep 15, 1997
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Abstract
A circuit for performing prefix computation in an asynchronous digital processor by implementing a serial process and a tree process for the same prefix computation in parallel. The first output from either processes is selected and used for the subsequent operation. For a prefix computation with N inputs, an average-case latency of O(loglog N) can be achieved. Buffering can be used for a full-throughout operation.
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