Caching in a multi-processor computer system
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United States of America Patent
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Dec 7, 1999
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N/A
app pub date -
May 18, 1998
filing date -
Jun 7, 1995
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Abstract
A structure and method of implementing a cache memory for a multi-processor system. The cache memory includes a main memory which is coupled to a main memory bus. A plurality of processors can also be coupled to the main memory bus. The main memory includes a plurality of RAM circuit module memory banks. The sense amplifiers of a predetermined number of banks are used as cache memory (i.e., sense amplifier cache lines). The number of banks used with sense amplifiers activated is substantially less than the total number of banks. The banks which are not used as cache memory are kept in a precharged state.
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