Hybrid tag architecture for a cache memory
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United States of America Patent
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Dec 7, 1999
Issued Date -
N/A
app pub date -
Aug 11, 1997
filing date -
Jan 20, 1995
priority date (Note) -
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Abstract
A cache memory system having a hybrid tag architecture and a series of data lines is disclosed. The cache memory includes a cache controller and a dirty tag memory included within the cache controller. The dirty tag memory indicates the status of each data line in the cache memory. A tag memory is coupled to the cache controller and is located external to the cache controller.
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