Apparatus for randomly sampling instructions in a processor pipeline
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United States of America Patent
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Dec 7, 1999
Grant Date -
N/A
app pub date -
Nov 26, 1997
filing date -
Nov 26, 1997
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An apparatus is provided for sampling instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus includes a fetch unit for fetching instructions into a first stage of the pipeline. Certain randomly selected instructions are identified, and state information of the system is sampled while a particular selected instruction is in any stage of the pipeline. Software is informed when the particular selected instruction leaves the pipeline so that the software can read any of the sampled state information.
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