NMOS input receiver circuit
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United States of America Patent
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-
Dec 14, 1999
Issued Date -
N/A
app pub date -
Nov 11, 1998
filing date -
Aug 15, 1994
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An input receiver circuit in a read-only memory is provided with a feedback to control hysteresis. A second stage and an additional output is added to the receiver. Switching circuit noise from inside of the read-only memory is isolated by the added state and outputs, and cannot be fed back into the receiver circuit to affect the detection of the TTL voltage levels. Use of wide and long FET sizes minimizes the manufacture related variations in the input receiver switching levels.
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