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Abstract

A digital PLL in uses pulse width detection to provide frequency/phase error correction for a DCO. A pulse width detector is implemented using fine and coarse detection circuits which provide selectable fine and coarse detection granularity. Both the fine and coarse detection circuits use a number of individual detector elements coupled in sequence--a phase error pulse propagates through the detector elements which quantize pulse width detection. Each detector element includes a pulse width detect latch that latches an phase error pulse width indication for the current cycle and the previous cycle. A comparator determines in each cycle whether the phase error pulse width has changed--a phase correction signal is generated if either (a) the fine detection circuit detects that the phase error pulse width is increasing, or (b) the course detection circuit detects that the phase error is not decreasing.

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