Latch-up prevention for memory cells
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United States of America Patent
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Dec 21, 1999
Grant Date -
N/A
app pub date -
Mar 20, 1998
filing date -
Mar 20, 1998
priority date (Note) -
Expired
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Abstract
An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to V.sub.cc through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.
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