Method of routing an integrated circuit
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United States of America Patent
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-
Dec 21, 1999
Grant Date -
N/A
app pub date -
Nov 1, 1996
filing date -
Nov 1, 1996
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method for automatically selecting tie styles used during the horizontal placement of substrate and well ties. A linear order of tie styles is determined (2422). Ties are placed horizontally in the layout based upon an initial tie style (2424). Route and compact layout components (2426). If the layout has satisfied the tie coverage rules (2428) the tie style selection process is complete. Otherwise, contacts, vias and ties are added where possible (2430). If the layout has now satisfied the tie coverage rules (2432) tie style selection process is complete. If not, the next tie style is chosen from the linear order (2434). The process continues by placing (2424), routing and compacting components (2426) with the new tie style, until the cell satisfies the tie coverage rules.
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Cited Art Landscape
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